A Practical Approach to Word Level Model Checking of Industrial Netlists

DOI10.1007/978-3-540-70545-1_43zbMath1155.68425OpenAlexW1551538037MaRDI QIDQ3512509

Per Bjesse

Publication date: 15 July 2008

Published in: Computer Aided Verification (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-70545-1_43

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Related Items (3)

Partial Order Reduction for Deep Bug Finding in Synchronous Hardware ⋮ Level-up -- from bits to words ⋮ Word level bitwidth reduction for unbounded hardware model checking

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