DPA Leakage Models for CMOS Logic Circuits

DOI10.1007/11545262_27zbMath1245.94086OpenAlexW2165637947MaRDI QIDQ3522138

Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa

Publication date: 29 August 2008

Published in: Cryptographic Hardware and Embedded Systems – CHES 2005 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11545262_27

Mathematics Subject Classification ID

Cryptography (94A60)

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Monomial evaluation of polynomial functions protected by threshold implementations -- with an illustration on AES -- extended version ⋮ Power Analysis to ECC Using Differential Power Between Multiplication and Squaring ⋮ Evolutionary ciphers against differential power analysis and differential fault analysis ⋮ Polar differential power attacks and evaluation ⋮ Secure hardware implementation of nonlinear functions in the presence of glitches ⋮ Side-channel resistant crypto for less than 2,300 GE ⋮ Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches ⋮ Practical Attacks on Masked Hardware ⋮ Wavelet scattering transform and ensemble methods for side-channel analysis

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