AES on FPGA from the Fastest to the Smallest

DOI10.1007/11545262_31zbMath1319.94063OpenAlexW1568970091MaRDI QIDQ3522144

Tim Good, Mohammed Benaissa

Publication date: 29 August 2008

Published in: Cryptographic Hardware and Embedded Systems – CHES 2005 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11545262_31

zbMATH Keywords

finite fieldfield programmable gate array (FPGA)advanced encryption standard (AES)low areahigh throughputdesign explorationapplication specific instruction processor (ASIP)pipelined

Mathematics Subject Classification ID

Cryptography (94A60)

Related Items (2)

Implementation of the AES-128 on Virtex-5 FPGAs ⋮ Chai-Tea, Cryptographic Hardware Implementations of xTEA

This page was built for publication: AES on FPGA from the Fastest to the Smallest