CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method

DOI10.1007/978-3-540-74735-2_25zbMath1391.94764OpenAlexW1603217046MaRDI QIDQ3525059

Tetsuya Izu, Jun Kogure, Takeshi Shimoyama

Publication date: 16 September 2008

Published in: Cryptographic Hardware and Embedded Systems - CHES 2007 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-74735-2_25

zbMATH Keywords

implementationFPGAinteger factorizationnumber field sieve method (NFS)sieving step

Mathematics Subject Classification ID

Cryptography (94A60) Primality (11Y11)

Related Items (3)

Computational hardness of IFP and ECDLP ⋮ Strategy of Relations Collection in Factoring RSA Modulus ⋮ CAIRN 2

This page was built for publication: CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method