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Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures - MaRDI portal

Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures

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Publication:3547697

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DOI10.1109/TIT.2004.833353zbMath1298.94144MaRDI QIDQ3547697

Guido Montorsi, Alberto Tarable, Sergio Benedetto

Publication date: 21 December 2008

Published in: IEEE Transactions on Information Theory (Search for Journal in Brave)

zbMATH Keywords

parallel implementation turbo codes memory mapping Low-density parity-check, codes (LDPC)

Mathematics Subject Classification ID

Combined modulation schemes (including trellis codes) in coding theory (94B12) Decoding (94B35)

Related Items (1)

Parallel access by butterfly networks for any degree permutation polynomial and ARP interleavers

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