On the operating unit size of load/store architectures

DOI10.1017/S0960129509990314zbMath1206.68114OpenAlexW2144055884MaRDI QIDQ3564342

Jan A. Bergstra, C. A. Middelburg

Publication date: 2 June 2010

Published in: Mathematical Structures in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1017/s0960129509990314

zbMATH Keywords

Maurer machines

Mathematics Subject Classification ID

Related Items (1)

Instruction sequence processing operators

Cites Work

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• Program algebra for sequential code
• Combining programs and state machines
• A theory of computer instructions
• Process Algebra
• Maurer computers for pipelined instruction processing
• A Theory of Computer Instructions

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