LOW-LATENCY CONNECTED COMPONENT LABELING USING AN FPGA

DOI10.1142/S0129054110007337zbMath1192.68771MaRDI QIDQ3569284

Koji Nakano, Yasuaki Ito

Publication date: 18 June 2010

Published in: International Journal of Foundations of Computer Science (Search for Journal in Brave)

zbMATH Keywords

image processingFPGAhardware algorithmconnected component labeling

Mathematics Subject Classification ID

Computing methodologies for image processing (68U10)

Cites Work

• Linear-time connected-component labeling based on sequential local operations
• Connectivity in Digital Pictures
• Concurrent determination of connected components

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