VLSI Physical Design: From Graph Partitioning to Timing Closure

DOI10.1007/978-90-481-9591-6zbMath1213.68009OpenAlexW1944814515WikidataQ63866313 ScholiaQ63866313MaRDI QIDQ3577051

Jens Lienig, Andrew B. Kahng, Jin Hu, Igor L. Markov

Publication date: 3 August 2010

Full work available at URL: https://doi.org/10.1007/978-90-481-9591-6

zbMATH Keywords

partitioningVLSI designroutingelectronic design automation (EDA)design automationelectronicsplacementchip planningphysical design algorithmstime closure

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Research exposition (monographs, survey articles) pertaining to computer science (68-02) Computer system organization (68M99)

Related Items (14)

An exact approach for the balanced \(k\)-way partitioning problem with weight constraints and its application to sports team realignment ⋮ Commutativity in double interchange semigroups ⋮ Parameterized Minimum Cost Partition of a Tree with Supply and Demand ⋮ Physical synthesis of quantum circuits using templates ⋮ MAX \(\kappa\)-cut and the inhomogeneous Potts spin Glass ⋮ Parameterized algorithms for graph partitioning problems ⋮ Optimal hierarchical clustering on a graph ⋮ Solving graph partitioning on sparse graphs: cuts, projections, and extended formulations ⋮ An annotated review on graph drawing and its applications ⋮ Partitioning \(P_4\)-tidy graphs into a stable set and a forest ⋮ Balanced graph partitioning based on mixed 0-1 linear programming and iteration vertex relocation algorithm ⋮ Lagrangian relaxation versus genetic algorithm based metaheuristic for a large partitioning problem ⋮ Solving SAT (and MaxSAT) with a quantum annealer: foundations, encodings, and preliminary results ⋮ An exact approach for the multi-constraint graph partitioning problem

This page was built for publication: VLSI Physical Design: From Graph Partitioning to Timing Closure