Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

DOI10.1007/978-3-642-15031-9_18zbMath1297.94068OpenAlexW1562434331MaRDI QIDQ3583462

Kris Gaj, Marcin Rogawski, Ekawat Homsirikamol

Publication date: 17 August 2010

Published in: Cryptographic Hardware and Embedded Systems, CHES 2010 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-15031-9_18

zbMATH Keywords

FPGAbenchmarkinghash functionsSHA-3

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Related Items (1)

Lightweight Implementations of SHA-3 Candidates on FPGAs

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