A dc I–V model for short‐channel polygonal enclosed‐layout transistors

DOI10.1002/CTA.537zbMath1156.94443OpenAlexW4254274046MaRDI QIDQ3615715

Beatriz Blanco-Filgueira, Johann Hauer, Diego Cabello, Paula López

Publication date: 24 March 2009

Published in: International Journal of Circuit Theory and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/cta.537

zbMATH Keywords

modellingdeep submicron CMOSenclosed-layout transistors (ELT)radiation-hardnessshort-channel effects

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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