Fault Analysis Attack against an AES Prototype Chip Using RSL

DOI10.1007/978-3-642-00862-7_29zbMath1237.94093OpenAlexW1483074993MaRDI QIDQ3623065

Tatsuya Yagi, K. Sakiyama, Kazuo Ohta

Publication date: 29 April 2009

Published in: Topics in Cryptology – CT-RSA 2009 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-00862-7_29

zbMATH Keywords

fault analysisAESclock-based attackrandom switching logic

Mathematics Subject Classification ID

Cryptography (94A60)

Cites Work

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• Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
• A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
• Elliptic Curve Cryptosystems
• Cryptographic Hardware and Embedded Systems - CHES 2004
• Changing the Odds Against Masked Logic
• Topics in Cryptology – CT-RSA 2005

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