A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems

DOI10.1007/978-3-540-89985-3_86zbMath1188.68078OpenAlexW284298418MaRDI QIDQ3628404

Fabrizio Lombardi, Zahra Mashreghian Arani, Masoud Hashempour

Publication date: 20 May 2009

Published in: Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-89985-3_86

zbMATH Keywords

bifurcationfault-tolerancecircuit modelnanotechnologymultiplexing

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Unnamed Item
• On the maximum tolerable noise for reliable computation by formulas

This page was built for publication: A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems