Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram

DOI10.1007/978-3-540-89985-3_85zbMath1188.68092OpenAlexW828287MaRDI QIDQ3628525

Masahiro Fujita, Bijan Alizadeh

Publication date: 20 May 2009

Published in: Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-89985-3_85

zbMATH Keywords

formal verificationsequential equivalence checkingsystem on chip and canonical representation

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• Verification of SpecC using predicate abstraction

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