FRGA Matching Algorithm in High-Speed Packet Switches
From MaRDI portal
Publication:3628598
DOI10.1007/978-3-540-89985-3_95zbMATH Open1188.68091OpenAlexW1773367870MaRDI QIDQ3628598
Mohammad Javad Rostami, Ali Asghar Khodaparast
Publication date: 20 May 2009
Published in: Communications in Computer and Information Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-540-89985-3_95
Nonnumerical algorithms (68W05) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)
Recommendations
- Title not available (Why is that?) π π
- Title not available (Why is that?) π π
- On iterative solutions for performance of high-speed switching networks π π
- Fast ping-pong arbitration for input-output queued packet switches π π
- Frame-Based Packet-Mode Scheduling for Input-Queued Switches π π
- Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing π π
- Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing π π
This page was built for publication: FRGA Matching Algorithm in High-Speed Packet Switches
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3628598)