A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions

DOI10.1007/978-3-642-04138-9_15zbMath1290.94122OpenAlexW1945373036WikidataQ58765214 ScholiaQ58765214MaRDI QIDQ3642935

Theo Kluter, Paolo Ienne, Stéphane Badel, Yusuf Leblebici, Alessandro Cevrero, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert

Publication date: 10 November 2009

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-04138-9_15

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Related Items (5)

Protecting secure ICs against side-channel attacks by identifying and quantifying potential EM and leakage hotspots at simulation stage ⋮ Physical attacks and beyond ⋮ Side-channel resistant crypto for less than 2,300 GE ⋮ Custom instruction support for modular defense against side-channel and fault attacks ⋮ Integrating side channel security in the FPGA hardware design flow

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