TCTL Model Checking of Time Petri Nets
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Publication:3656779
DOI10.1093/logcom/exp036zbMath1188.68182OpenAlexW2105389929MaRDI QIDQ3656779
Hanifa Boucheneb, Guillaume Gardey, Olivier H. Roux
Publication date: 14 January 2010
Published in: Journal of Logic and Computation (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1093/logcom/exp036
Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)
Related Items (13)
Delay-dependent partial order reduction technique for real time systems ⋮ Shrinking of time Petri nets ⋮ Symbolic State Space of Stopwatch Petri Nets with Discrete-Time Semantics (Theory Paper) ⋮ Design and verification of pipelined circuits with timed Petri nets ⋮ Comparing the Expressiveness of Timed Automata and Timed Extensions of Petri Nets ⋮ Relevant Timed Schedules / Clock Valuations for Constructing Time Petri Net Reachability Graphs ⋮ TCTL-preserving translations from timed-arc Petri nets to networks of timed automata ⋮ Relevant timed schedules/clock vectors for constructing time Petri net reachability graphs ⋮ Verification of Timed-Arc Petri Nets ⋮ Time based deadlock prevention for Petri nets ⋮ Maximally permissive controller synthesis for time Petri nets ⋮ Timed Aggregate Graph: A Finite Graph Preserving Event- and State-Based Quantitative Properties of Time Petri Nets ⋮ Timed Petri nets with reset for pipelined synchronous circuit design
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