Parallel multipliers with NOR gates based on G-minimum adders

DOI10.1007/BF00978712zbMath0562.94019MaRDI QIDQ3676064

Saburo Muroga, Ging-Shung Yu

Publication date: 1984

Published in: International Journal of Computer & Information Sciences (Search for Journal in Brave)

zbMATH Keywords

logic designparallel multipliersNOR gates

Mathematics Subject Classification ID

Cites Work

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• Minimum Parallel Binary Adders with NOR (NAND) Gates
• Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
• Majority Gate Networks

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