A VLSI design for the parallel finite state automaton and its performance evaluation as a hardware scanner

DOI10.1007/BF00985824zbMath0563.94025MaRDI QIDQ3677666

Ali R. Hurson

Publication date: 1984

Published in: International Journal of Computer & Information Sciences (Search for Journal in Brave)

zbMATH Keywords

VLSI designperformance evaluationpattern matchinghardware architecturehardware scannerparallel finite state automaton

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80)

Cites Work

• A class of systolic multiplier units for VLSI technology
• Multiple Match Resolvers: A New Design Method
• Efficient string matching
• Automatic generation of efficient lexical processors using finite state techniques
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