Square-Rooting Algorithms for High-Speed Digital Circuits

DOI10.1109/TC.1985.1676618zbMath0565.68040OpenAlexW2074838321MaRDI QIDQ3680276

Stanisław Majerski

Publication date: 1985

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1985.1676618

zbMATH Keywords

binary square rootingparallel reduction of summandsredundant number notation

Mathematics Subject Classification ID

Symbolic computation and algebraic computation (68W30)

Related Items (3)

Optimal absolute error starting values for Newton-Raphson calculation of square root ⋮ Reciprocal and reciprocal square root units with operand modification and multiplication ⋮ On exponential convergence of nonlinear gradient dynamics system with application to square root finding

This page was built for publication: Square-Rooting Algorithms for High-Speed Digital Circuits