High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

DOI10.1109/TC.1985.1676634zbMath0565.94021MaRDI QIDQ3680755

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

Publication date: 1985

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

arithmetic operationshardware algorithmredundant binary representationhigh-speed multiplierbinary integer multiplicationcarry-propagation-free addersigned-digit number representation

Mathematics Subject Classification ID

Symbolic computation and algebraic computation (68W30) Mathematical problems of computer architecture (68M07)

Related Items (3)

Redundant integer representations and fast exponentiation ⋮ On the distribution of runs of ones in binary strings ⋮ Real-time arithmetic unit

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