VLSI Architectures for Computing Multiplications and Inverses in GF(2m)

DOI10.1109/TC.1985.1676616zbMath0566.94019OpenAlexW1889596231WikidataQ45960884 ScholiaQ45960884MaRDI QIDQ3682399

Leslie J. Deutsch, Charles C. Wang, Jim K. Omura, Howard M. Shao, Irving S. Reed, Trieu-Kien Truong

Publication date: 1985

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1985.1676616

zbMATH Keywords

VLSIsystolic arraypipeline structureMassey-Omura multiplierFinite field arithmetic logic

Mathematics Subject Classification ID

Theory of error-correcting codes and error-detecting codes (94B99) Software, source code, etc. for problems pertaining to field theory (12-04)

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