Optimal Three-Layer Channel Routing

DOI10.1109/TC.1984.1676459zbMath0567.94029OpenAlexW1940955666MaRDI QIDQ3684051

Witold jun. Lipski, Franco P. Preparata

Publication date: 1984

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1984.1676459

zbMATH Keywords

algorithmVLSI designVLSI layoutsmultilayer wiring

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15)

Related Items (18)

Channel routing in knock-knee mode: Simplified algorithms and proofs ⋮ Diagonal channel routing with vias at unit distance ⋮ Geometric problems on two-dimensional array processors ⋮ Optimizing area for three-layer knock-knee channel routing ⋮ Wiring layouts in the tri-hexagonal grid^∗ ⋮ A unified approach to layout wirability ⋮ Optimal multilayer channel routing with overlap ⋮ Routing in times square mode ⋮ Minimum-diameter cyclic arrangements in mapping data-flow graphs onto VLSI arrays ⋮ An efficient parallel logarithmic time algorithm for the channel routing problem ⋮ Parity conditions in homotopic knock-knee routing ⋮ Maximum \(k\)-covering of weighted transitive graphs with applications ⋮ Dynamic computational geometry on meshes and hypercubes ⋮ MINIMUM NUMBER OF PIECES IN A CONVEX PARTITION OF A POLYGONAL DOMAIN ⋮ A preliminary study of a diagonal channel-routing model ⋮ Optimal algorithms for adjacent side routing ⋮ Routings for involutions of a hypercube ⋮ Algorithms for routing in planar graphs

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