A class of systolic multiplier units for VLSI technology

DOI10.1007/BF00987038zbMath0591.94033OpenAlexW2014644372MaRDI QIDQ3720474

No author found.

Publication date: 1985

Published in: International Journal of Computer & Information Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf00987038

zbMATH Keywords

VLSI designmultiplication algorithmpipeline architecture

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

Related Items (1)

A VLSI design for the parallel finite state automaton and its performance evaluation as a hardware scanner

Cites Work

• The Area-Time Complexity of Binary Multiplication
• A Proof of the Modified Booth's Algorithm for Multiplication
• A Compact High-Speed Parallel Multiplication Scheme
• Majority Gate Networks
• A SIGNED BINARY MULTIPLICATION TECHNIQUE

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