Minced trees, with applications to fault-tolerant VLSI processor arrays

DOI10.1007/BF01704902zbMath0602.68055OpenAlexW2032665599MaRDI QIDQ3738575

Arnold L. Rosenberg, Fan R. K. Chung

Publication date: 1986

Published in: Mathematical Systems Theory (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01704902

zbMATH Keywords

binary treegraph-embeddingdesign of fault-tolerant VLSI processor arrays

Mathematics Subject Classification ID

Trees (05C05) Graph theory (including graph drawing) in computer science (68R10) Planar graphs; geometric and topological aspects of graph theory (05C10)

Cites Work

• Cost Trade-offs in Graph Embeddings, with Applications
• A Graph Model for Fault-Tolerant Computing Systems

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