An Array Layout Methodology for VLSI Circuits

DOI10.1109/TC.1986.1676713zbMath0604.94017OpenAlexW2083419902MaRDI QIDQ3743256

John P. Hayes, Musaravakkam S. Krishnan

Publication date: 1986

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1986.1676713

zbMATH Keywords

VLSI designminimum spanning treetree networksintegrated circuit layoutAlgorithms for optimal array realizationarea-efficient layoutslayout complexitylayout slices

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15)

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