OR Practice—Lagrangian Relaxation for Testing Infeasibility in VLSI Routing

DOI10.1287/opre.34.6.819zbMath0629.94030OpenAlexW2076646020MaRDI QIDQ3767269

Dorit S. Hochbaum, Thomas A. Feo

Publication date: 1986

Published in: Operations Research (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1287/opre.34.6.819

zbMATH Keywords

Lagrangian relaxationshortest pathVLSI circuit design

Mathematics Subject Classification ID

Programming involving graphs or networks (90C35) Integer programming (90C10) Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)

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