Configuration of VLSI Arrays in the Presence of Defects

DOI10.1145/1634.2377zbMath0632.94033OpenAlexW4212788429MaRDI QIDQ3770454

No author found.

Publication date: 1984

Published in: Journal of the ACM (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1145/1634.2377

zbMATH Keywords

systolic arraysprobabilistic analysisfault tolerancepercolation theorywire lengthwafer-scale integrationVLSI arrayscircuit areaqueuing processes

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Applications of graph theory to circuits and networks (94C15)

Related Items

Counting the number of fault patterns in redundant VLSI arrays ⋮ Fault-tolerance VLSI sorters ⋮ Catastrophic faults in reconfigurable systolic linear arrays ⋮ Testing and reconfiguration of VLSI linear arrays ⋮ Maintaining bipartite matchings in the presence of failures ⋮ Flow in planar graphs with vertex capacities