Linear placement algorithms and applications to VLSI design

DOI10.1002/net.3230170406zbMath0642.90059OpenAlexW2060067940MaRDI QIDQ3783832

Chung-Kuan Cheng

Publication date: 1987

Published in: Networks (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1002/net.3230170406

zbMATH Keywords

job sequencingpolynomial-time algorithmheuristic algorithmnetwork flowVLSI placementparallel graphsdesign of integrated circuitsliner placement techniquesum of wiring lengthsVery Large Scale Integrated Circuits

Mathematics Subject Classification ID

Numerical mathematical programming methods (65K05) Deterministic scheduling theory in operations research (90B35) Production models (90B30)

Related Items (3)

Fast simulated annealing for single-row equidistant facility layout ⋮ Efficient algorithms for single- and two-layer linear placement of parallel graphs ⋮ Molecular solution to the optimal linear arrangement problem based on DNA computation

Cites Work

• One-dimensional logic gate assignment and interval graphs
• An Efficient Heuristic Procedure for Partitioning Graphs
• Single-Machine Job Sequencing with Treelike Precedence Ordering and Linear Delay Penalties

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