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Project verification and construction of superchip tests at the RTL level - MaRDI portal

Project verification and construction of superchip tests at the RTL level

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Publication:384503

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DOI10.1134/S0005117913010104zbMath1322.94129MaRDI QIDQ384503

L. A. Zolotorevich

Publication date: 27 November 2013

Published in: Automation and Remote Control (Search for Journal in Brave)

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Cites Work

Development of tests for VLSI circuit testability at the upper design levels

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