Syndrome-Testable Design of Combinational Circuits

DOI10.1109/TC.1980.1675603zbMath0436.94039OpenAlexW1967664042MaRDI QIDQ3877576

Jacob Savir

Publication date: 1980

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1980.1675603

zbMATH Keywords

prime implicantcombinational circuitstuck-at faultsingle faultmintermfan-out-free circuit

Mathematics Subject Classification ID

Related Items (5)

Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing ⋮ Orthogonal algorithm of logic probability and syndrome-testable analysis ⋮ BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count ⋮ Quick detection of faults in combinational networks designed in minterm format by computing a single novel parameter ⋮ Minimal length test vectors for multiple-fault detection

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