LSI logic testing — An overview
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Publication:3904528
DOI10.1109/TC.1981.6312152zbMath0455.94036OpenAlexW2004197874MaRDI QIDQ3904528
Anil D. Savkar, Eugen I. Muehldorf
Publication date: 1981
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1981.6312152
test pattern generationlarge scale integrationfault modelingBoolean differencefault simulationpath sensitization
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A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits ⋮ Functional test generation using binary decision diagrams ⋮ Graph partitioning applied to the logic testing of combinational circuits ⋮ Efficient VLSI fault simulation
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