An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits

DOI10.1109/TC.1981.1675757zbMath0455.94038OpenAlexW2149107969MaRDI QIDQ3904532

Prabhakar Goel

Publication date: 1981

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1981.1675757

zbMATH Keywords

test generationerror correctionstuck faultsuntestable fault

Mathematics Subject Classification ID

Related Items (8)

Selective I/O scan: A diagnosable design technique for VLSI systems ⋮ A complete critical path algorithm for test generation of combinational circuits ⋮ Propagation based local search for bit-precise reasoning ⋮ Parallel VLSI test in a shared-memory multiprocessor ⋮ Constraint satisfaction using constraint logic programming ⋮ Confidence intervals for expected coverage from a beta testability model ⋮ Forecasting the efficiency of test generation algorithms for combinational circuits ⋮ Thread-parallel integrated test pattern generator utilizing satisfiability analysis

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