A design of programmable logic arrays with universal tests

DOI10.1109/TCS.1981.1084932zbMath0461.94020OpenAlexW2128541587MaRDI QIDQ3912733

K. Kinoshita, Hideo Fujiwara

Publication date: 1981

Published in: IEEE Transactions on Circuits and Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcs.1981.1084932

zbMATH Keywords

fault detectionlogic circuitsfault locationuniversal test sets

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (3)

Easy test generation PLAs ⋮ A testable design of programmable logic arrays with universal control and minimal overhead ⋮ Computations over finite monoids and their test complexity

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