The Weighted Syndrome Sums Approach to VLSI Testing

DOI10.1109/TC.1981.1675744zbMath0465.94046OpenAlexW1845462324MaRDI QIDQ3918055

Jacob Savir, Zeev Barzilai, George Markowsky, Merlin G. Smith

Publication date: 1981

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1981.1675744

zbMATH Keywords

partitioningself-testingsyndrome-testable design

Mathematics Subject Classification ID

Related Items (3)

A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits ⋮ The use of linear sums in exhaustive testing ⋮ Graph partitioning applied to the logic testing of combinational circuits

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