A Regular Layout for Parallel Adders
From MaRDI portal
Publication:3934311
DOI10.1109/TC.1982.1675982zbMath0477.94037OpenAlexW2168543008WikidataQ55953421 ScholiaQ55953421MaRDI QIDQ3934311
Publication date: 1982
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1982.1675982
VLSI architecturecombinational logicprefix computationmodels of computationparallel additioncircuit designarea-time complexityparallel polynomial evaluationcarry lookahead
Related Items (21)
Formal verification of parallel prefix sum and stream compaction algorithms in CUDA ⋮ A chained-matrices approach for parallel computation of continued fractions and its applications ⋮ An easily testable optimal-time VLSI-multiplier ⋮ The applicability of discrete performance estimation methods to VLSI design ⋮ Communication-efficient parallel algorithms for distributed random-access machines ⋮ A search for Wilson primes ⋮ A software interface and hardware design for variable-precision interval arithmetic ⋮ OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES ⋮ Parallel evaluation of arithmetic circuits ⋮ Formal proof of integer adders using all-prefix-sums operation ⋮ Formal proof of prefix adders ⋮ The complexity of a VLSI adder ⋮ Computations over finite monoids and their test complexity ⋮ Mod \(m\) arithmetic in binary systems ⋮ Non-associative parallel prefix computation ⋮ Parallel prefix computation with few processors ⋮ Limited width parallel prefix circuits ⋮ Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems ⋮ A novel parallel prefix adder for optimized radix-2 FFT processor ⋮ Chai-Tea, Cryptographic Hardware Implementations of xTEA ⋮ A fully parallel algorithm for residue to binary conversion
This page was built for publication: A Regular Layout for Parallel Adders
