Parallel architectures for RLS with directional forgetting
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Publication:3974117
DOI10.1002/acs.4480010106zbMath0737.93081OpenAlexW2059091254MaRDI QIDQ3974117
Publication date: 25 June 1992
Published in: International Journal of Adaptive Control and Signal Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1002/acs.4480010106
systolic arraysadaptive signal processingself-tuning control\(UD\) algorithmrecursive least squares with directional forgetting
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