Minimizing total wire length during 1-dimensional compaction

DOI10.1016/0167-9260(92)90023-RzbMath0758.94023OpenAlexW2036218749MaRDI QIDQ4015505

Susanne E. Hambrusch, Hung-Yi Tu

Publication date: 13 January 1993

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(92)90023-r

zbMATH Keywords

analysis of algorithmsconstraint graphwire lengthVLSI layout design1-dimensional compactionlayout width

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Applications of graph theory to circuits and networks (94C15)

Related Items (1)

New algorithms for mimizing the longest wire length during circuit compaction.

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