Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange Network

DOI10.1109/TC.1976.1674637zbMath0324.68036OpenAlexW2081568423MaRDI QIDQ4088287

Tomas Lang

Publication date: 1976

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1976.1674637

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Formal languages and automata (68Q45)

Related Items (3)

Routing, merging, and sorting on parallel models of computation ⋮ An optimal time bound for oblivious routing ⋮ Oblivious routing with limited buffer capacity

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