High-speed \(\mathrm{RS}(255, 239)\) decoder based on LCC decoding

DOI10.1007/s00034-011-9327-4zbMath1237.94140OpenAlexW2075311861MaRDI QIDQ411184

F. García-Herrero, Pramod Kumar Meher, Javier Valls

Publication date: 4 April 2012

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-011-9327-4

zbMATH Keywords

Reed-Solomon codesASIC implementationFPGA implementationlow complexity chase decodersoft-decision decoding

Mathematics Subject Classification ID

Decoding (94B35)

Cites Work

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• Towards a VLSI architecture for interpolation-based soft-decision Reed-Solomon decoders
• Algebraic Codes on Lines, Planes, and Curves
• Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed–Solomon Decoding
• Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information
• Efficient decoding of Reed-Solomon codes beyond half the minimum distance
• Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part II: Soft-Input Soft-Output Iterative Decoding
• Class of algorithms for decoding block codes with channel measurement information

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