A Compact High-Speed Parallel Multiplication Scheme
From MaRDI portal
Publication:4145290
DOI10.1109/TC.1977.1674730zbMath0368.94037OpenAlexW2112637319MaRDI QIDQ4145290
William J. Kubitz, William J. Stenzel, Gilles H. Garcia
Publication date: 1977
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1977.1674730
Related Items (2)
A class of systolic multiplier units for VLSI technology ⋮ Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems
This page was built for publication: A Compact High-Speed Parallel Multiplication Scheme