The complexity of VLSI power-delay optimization by interconnect resizing

DOI10.1007/S10878-010-9355-1zbMath1243.90188OpenAlexW2159175454MaRDI QIDQ421260

Shmuel Wimer, Konstantin Moiseev, Avinoam Kolodny

Publication date: 23 May 2012

Published in: Journal of Combinatorial Optimization (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10878-010-9355-1

zbMATH Keywords

NP-completenessVLSI interconnectspower-delay optimization

Mathematics Subject Classification ID

Abstract computational complexity for mathematical programming problems (90C60) Combinatorial optimization (90C27)

Related Items (2)

The complexity of VLSI power-delay optimization by interconnect resizing ⋮ On VLSI interconnect optimization and linear ordering problem

Cites Work

• The complexity of VLSI power-delay optimization by interconnect resizing

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