On-line testing for VLSI: state of the art and trends

DOI10.1016/S0167-9260(98)00028-5zbMath0908.68076OpenAlexW2071482811MaRDI QIDQ4225371

Michael Nicolaidis

Publication date: 12 January 1999

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0167-9260(98)00028-5

zbMATH Keywords

soft errorson-line testinghardware fault toleranceself-checking circuitsdeep submicron scalingfail-safe circuitson-line current monitoringperturbation hardened circuits

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Uses Software

• SEC-DED

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