On the optimal four-way switch box routing structures of FPGA greedy routing architectures

DOI10.1016/S0167-9260(98)00011-XzbMath0909.68105WikidataQ127087505 ScholiaQ127087505MaRDI QIDQ4225389

Yu-Liang Wu, C. K. Wong, Jiaofeng Pan, Gui Ying Yan

Publication date: 12 January 1999

Published in: Integration (Search for Journal in Brave)

zbMATH Keywords

FPGA routing architecture

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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