A reconfigurable analog VLSI neural network architecture with non-linear synapses

DOI<link itemprop=identifier href="https://doi.org/10.1002/(SICI)1097-007X(199805/06)26:3<307::AID-CTA14>3.0.CO;2-5" /><307::AID-CTA14>3.0.CO;2-5 10.1002/(SICI)1097-007X(199805/06)26:3<307::AID-CTA14>3.0.CO;2-5zbMath0915.68141OpenAlexW2036420215MaRDI QIDQ4226496

No author found.

Publication date: 22 June 1999

Full work available at URL: https://doi.org/10.1002/(sici)1097-007x(199805/06)26:3<307::aid-cta14>3.0.co;2-5

zbMATH Keywords

VLSI neural network architecture

Mathematics Subject Classification ID

Learning and adaptive systems in artificial intelligence (68T05) Neural networks for/in biological studies, artificial life and related topics (92B20) Circuits, networks (94C99)

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