Reconciling fault-tolerant distributed computing and systems-on-chip

DOI10.1007/S00446-011-0151-7zbMath1284.68071OpenAlexW2167308418MaRDI QIDQ424907

Matthias Függer, Ulrich Schmid

Publication date: 7 June 2012

Published in: Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00446-011-0151-7

zbMATH Keywords

VLSIclock synchronizationmodeling approachesfault-tolerant distributed systems

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Distributed systems (68M14) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Related Items (6)

HEX: scaling honeycombs is easier than scaling clock trees ⋮ Rigorously modeling self-stabilizing fault-tolerant circuits: an ultra-robust clocking scheme for systems-on-chip ⋮ On specifications and proofs of timed circuits ⋮ Accuracy of Message Counting Abstraction in Fault-Tolerant Distributed Algorithms ⋮ Self-stabilizing Byzantine clock synchronization with optimal precision ⋮ Fault-tolerant algorithms for tick-generation in asynchronous logic

Uses Software

• VINAS-P

Cites Work

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• Consensus algorithms with one-bit messages
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• Optimal precision in the presence of uncertainty
• Compiling communicating processes into delay-insensitive VLSI circuits
• On the existence of delay-insensitive fair arbiters: Trace theory and its limitations
• Buridan's principle
• The Theta-Model: achieving synchrony without clocks
• A theory of clock synchronization (extended abstract)
• Distributed order scheduling and its application to multi-core dram controllers
• Optimal and efficient clock synchronization under drifting clocks
• Impossibility of distributed consensus with one faulty process
• General theory of metastable operation
• Optimal Clock Synchronization under Different Delay Assumptions

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