Understanding retiming through maximum average-delay cycles

DOI10.1007/BF01187093zbMath0798.68055OpenAlexW4238478983MaRDI QIDQ4277377

Marios C. Papaefthymiou

Publication date: 31 October 1994

Published in: Mathematical Systems Theory (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01187093

zbMATH Keywords

synchronous circuitcombinational circuitryminimum clock periodunit-delay circuitry

Mathematics Subject Classification ID

Circuits, networks (94C99) Distributed algorithms (68W15)

Cites Work

• Retiming synchronous circuitry
• New scaling algorithms for the assignment and minimum mean cycle problems
• A characterization of the minimum cycle mean in a digraph
• On the capabilities of systolic systems
• Faster Scaling Algorithms for Network Problems
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