A methodology for hardware verification based on logic simulation

DOI10.1145/103516.103519zbMath0809.94035OpenAlexW2000040332MaRDI QIDQ4302838

Randal E. Bryant

Publication date: 30 March 1995

Published in: Journal of the ACM (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1145/103516.103519

zbMATH Keywords

hardware verificationternary simulationlogic simulationcircuit verification

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Specification and verification (program logics, model checking, etc.) (68Q60)

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