Efficient construction of catastrophic patterns for VLSI reconfigurable arrays

DOI10.1016/0167-9260(93)90049-IzbMath0808.94033OpenAlexW1984919959MaRDI QIDQ4307637

Amiya Nayak, Linda Pagli, Nicola Santoro

Publication date: 4 October 1994

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(93)90049-i

zbMATH Keywords

systolic arraystestingVLSIreconfigurationcatastrophic fault patterns

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (5)

Characterization of catastrophic faults in two-dimensional reconfigurable systolic arrays with unidirectional links ⋮ An improved testing scheme for catastrophic fault patterns ⋮ Testing and reconfiguration of VLSI linear arrays ⋮ Multi-level dynamo and opinion spreading ⋮ On enumeration of catastrophic fault patterns

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