Area-time efficient modulo 2/sup n/-1 adder design

DOI10.1109/82.298378zbMath0815.68015OpenAlexW2082239458MaRDI QIDQ4317362

J. Kalamatianos, Dimitris Nikolos, Costas Efstathiou

Publication date: 31 January 1995

Published in: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/82.298378

zbMATH Keywords

carry look-ahead adderscarry look-ahead addition algorithmsendaround carry addersmodulo \(2^ n- 1\) addersVLSI adders

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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