Scheduling with register constraints for DSP architectures

DOI10.1016/0167-9260(94)90013-2zbMath0875.68154OpenAlexW2074328793MaRDI QIDQ4331999

Gert Goossens, Hugo J. De Man, Francis Depuydt

Publication date: 27 February 1997

Published in: Integration (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-9260(94)90013-2

zbMATH Keywords

SchedulingRegister allocationRetimingExecution orderingReal-time signal processingRetargetable code generation

Mathematics Subject Classification ID

Computer system organization (68M99)

Uses Software

• LINDO

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